The precision machining of single crystal silicon and of layers deposited on such single crystal substrate is important for the production of many opto-electronic components. Typically during the processing of substrates, such as a multi-chip module substrates, precision machined features are required for applications such as the mounting of optical components, e.g. fibres, ball lenses or fabrication of sensors. On the substrate, electrical circuits are defined by the provision of both high and low impedance conducting patterns.
The optical component may be a ball lens mounted in an etched pit, or a graded index lens or an end of an optical fibre which is mounted in an etched groove. Further examples of an optical component that may be located in this way is an optical isolator or a planar waveguide component. One of the advantages of this form of location of an optical component is the dimensional stability it is likely to afford in relation to the electro-optic component and a further advantage is the precision of positioning it can afford.
One method of machining silicon is the crystallographic etching of a v-groove. A photolithographic process is used to define a mask in typically silicon nitride over the single crystal substrate. An anisotropic etch process may then be used to produce a v-groove in the substrate. Typically the processing of the substrate would begin with masking and anisotropic etching steps to form a pattern of v-grooves or pits across the substrate. After the etching, further processing is required to form a pattern for conductive circuits and component mounting sites. There are considerable advantages to machining the silicon at the end of the module fabrication process, which are principally due to the difficulty of accurately patterning subsequent layers when the substrate is no longer substantially flat. Considerable variations in photoresist thickness can occur due to the presence of such features leading to inaccurate patterning.
The presence of both high and low impedance electrical interconnects is often a requirement of such opto-electronic modules. High impedance interconnects conventionally require a considerable dielectric thickness. Although fabrication would be possible with inorganic dielectrics this is undesirable due to the problems associated with depositing and patterning these thick layers. In this respect we have employed an organic dielectric greatly simplifying the fabrication of the high impedance circuitry.
A final passivating layer of inorganic dielectric is required over the high impedance interconnect level and the organic dielectric. There is a difficulty which arises from the deposition and patterning of the high impedance interconnect and this passivating layer. That is the removal of unwanted metal and dielectric over the wettable pad layers, low impedance dielectric and any exposed silicon which would cause damage to these sensitive layers.
For the most part silicon etches are aggressive to most materials. Even for materials which are not readily attacked by etchants any exposed interfaces may prove to be an area of weakness. Such areas are frequently found when coating levels of appreciable topography with an inorganic dielectric. Such an area is the edge of the high impedance dielectric. An inorganic dielectric protection layer is used which can be patterned to selectively protect the substrate. After solder deposition and silicon etching this protection layer may be stripped in an oxygen based plasma without adversely affecting any other layers. This protection layer has the advantage of allowing the module to be completed without any further photolithographic stages after deposition of the solder or machining of the silicon.
The present invention is directed to an improved process for the definition of etched features on a silicon substrate.